The state of the art in power converters provides an adjustable voltage and frequency to the output through a pulse width modulated (PWM, pulse width modulation) voltage source inverter drive. Power converters can be used in uninterruptible power supplies (UPS), electric motors, etc. The PWM command is used in the power converter for controlling power to inertial electrical devices, made practical by modern electronic power switches. The duty cycle of a switch (ratio of on-time to total cycle time) is varied to achieve a desired average output voltage, current etc., when averaged over time.
A typical power converter is a switching power converter. It has two or more power semiconductor devices such as power semiconductor switches. The power semiconductor switches can, for example, be implemented by insulated-gate bipolar transistors (IGBT). As the switching speed of such semiconductor switches increase and currents increase, it becomes increasingly difficult to limit turn-off voltages to a permissible range. Should the permissible voltage across the controlled path of a semiconductor switch be exceeded, it will be destroyed. A particularly critical case is that of a short circuit, where the rate of current change di/dt induces in the stray inductances a voltage which is added to the voltage present in any case. The resultant overvoltage can exceed the permissible voltages, particularly across the controlled path of the semiconductor switch.
One approach to addressing the overvoltage is to increase the size of the resistor at the gate of the semiconductor switch. However, in order for this to be effective, the size of the resistor becomes too great and switching losses become unacceptable. Another method is to feedback the collector-emitter voltage to the gate of the semiconductor switch in order to maintain it in the on-state for a time determined by stray inductances in the high power circuit. The rise in the gate voltage limits the rise in the collector-emitter voltage. However, this method is largely ineffective due to the significant delay between the gate voltage falling below the Miller plateau and the rise of the collector-emitter voltage.
Another approach is to provide an active clamp, such as described in U.S. Pat. No. 7,119,586. Here, the active clamp is incorporated in the circuit between the semiconductor switch's collector and the input to the gate driver stage. This active clamp determines the voltage across the emitter-collector path of the semiconductor switch, and in this manner detects the beginning of the cut-off state, thereby freezing the instantaneous value of the switching signal. Since the semiconductor switch remains longer at the voltage level of the Miller Plateau, a small rate of current change di/dt of the collector current is achieved when turning-off particularly high voltages. This method of active clamping tends to result in a change in collector current slope without significantly increasing switching losses.
It is an aim of the present invention to address one or more of these issues with the prior art.
In a first aspect of the invention there is provided a control circuit for control of a semiconductor switching device comprising a first feedback path between a first electrode and a control electrode of said semiconductor switching device, said first feedback path comprising a capacitance, said control circuit being operable such that the capacitance in the first feedback path is dependent on the voltage level at said first electrode.
In a second aspect of the invention there is provided a control circuit for control of a semiconductor switching device comprising a first feedback path between a first electrode and a control electrode of said semiconductor switching device and comprising a capacitance, said control circuit being operable such that a feedback signal begins to flow in the first feedback path immediately as the semiconductor switching device begins switching off, thereby causing a control action on said semiconductor switching device.
Other optional aspects are as disclosed in the appended dependent claims.